The panel display device, such as the Liquid Crystal Display (LCD) and the Organic Light Emitting Display (OLED) comprises a plurality of pixels aligned in array. Each pixel generally comprises sub pixels of red, green, blue, three colors. Each sub pixel is controlled by one gate line and one data line. The gate line is employed to control the on and off of the sub pixel, and the data line applies various data voltage signals to make the sub pixel show various gray scales, and thus for realizing the full color image display.
With the development of the display technology, the requirements of the people to the display qualities of the display device, such as the display brightness, the color reduction, the richness of the image color gets higher and higher. The display merely utilizing the red, green and blue, three primary colors can no longer satisfy the requirements of the people to the display device. Thereafter, the four colors display device having red, green, blue, white four colors is proposed. One white sub pixel is added in each pixel for forming the RGBW pixel structure constructed by the red sub pixel (R), the green sub pixel (G), the blue sub pixel (B) and the white sub pixel (W). In the same display image, the display device utilizing the RGBW pixel structure has the larger pixel pitch than the display device utilizing the RGB three colors sub pixels structure, and the added white sub pixel has high transmission rate. The RGBW four colors sub pixels structure display device has benefits of high transmission rate and high aperture ratio, and is pursued by the consumers.
Please refer to FIG. 1, which is a circuit structure diagram of the demultiplex type display driving circuit used in a RGBW four colors pixel structure display device according to prior art. The circuit comprises: a plurality of drive units, and each drive unit comprises: a demultiplex module 10′, first, second, third and fourth data lines D1′-D4′ which are mutually parallel, sequentially aligned and vertical, and sub pixels 20′ of multiple rows, four columns, which are aligned in array; each sub pixel 20′ is electrically coupled to the data line corresponded with the column where the sub pixel 20′ is; specifically, the demultiplex module 10′ comprises: first, second, third and fourth thin film transistors T1′, T2′, T3′, T4′; gates of the first, the second, the third and the fourth thin film transistors T1′, T2′, T3′, T4′ are electrically coupled to first, second, third and fourth branch control signals Demux1′, Demux2′, Demux3′ and Demux4′, respectively, and sources are all electrically coupled to a data signal Input, and drains are electrically coupled to first, second, third and fourth data lines D1, D2′, D3′ and D4′, respectively. The circuit can control the waveforms of the four branch control signals to respectively activate the four thin film transistors to achieve the one to four division function of the data signal Input. However, the amount of the branch control signals are many, which will increase the loading of the control signal Integrated Circuit (IC), and meanwhile the feedthrough effect occurs to the pixel while the thin film transistor is deactivated to make the outputted data signal unstable.
Please refer to FIG. 2, which is a circuit structure diagram of a demultiplex type display driving circuit used in another RGBW four colors pixel structure display device according to prior art. The circuit comprises: a plurality of drive units, and each drive unit comprises: a demultiplex module 10″, first, second, third and fourth data lines D1″-D4″ which are mutually parallel, sequentially aligned and vertical, and sub pixels 20″ of multiple rows, four columns, which are aligned in array; each sub pixel 20″ is electrically coupled to the data line corresponded with the column where the sub pixel 20″ is; specifically, the demultiplex module 10″ comprises: first, second, third and fourth Transmission Gates TG1′, TG2′, TG3′, TG4′; the high voltage levels control ends of the first, the second, the third and the fourth Transmission Gates TG1′, TG2′, TG3′, TG4′ are electrically coupled to first, second, third and fourth branch control signals Demux1″, Demux2″, Demux3″ and Demux4″, respectively, and the low voltage level control ends are electrically coupled to fifth, sixth, seventh and eighth branch control signals Demux5″, Demux6″, Demux7″ and Demux8″, respectively, all the input ends are electrically coupled to the data signal Input, and the output ends are respectively coupled to first, second, third and fourth data lines D1″, D2″, D3″ and D4″, respectively; the first branch control signal Demux1″ and the fifth branch control signal Demux5″ are inverse in phase, and the second branch control signal Demux2″ and the sixth branch control signal Demux6″ are inverse in phase, and the third branch control signal Demux3″ and the seventh branch control signal Demux7″ are inverse in phase, and the fourth branch control signal Demux4″ and the eighth branch control signal Demux8″ are inverse in phase. The circuit can control the waveforms of the eight branch control signals to respectively activate the four CMOS transmission gates to achieve the one to four division function of the data signal Input, and raise the charge rate of the pixel for stabilizing the pixel voltage. However, the circuit increases the amount of the branch control signals in advance, which tremendously increase the loading of the control signal IC.